1. Field of the Invention
The present invention relates generally to integrated circuits, and more specifically to a method for fabricating polycrystalline silicon resistor structures therein.
2. Description of the Prior Art
CMOS SRAMs often use a four transistor cell design having resistive load devices. This design is used in order to save chip layout area over the traditional six transistor cell design. Two N-channel transistors are used to form a cross-coupled latch, while two additional N-channel transistors are used to provide access to the cell for reading and writing data. Two load devices are connected between the N-channel transistors in the latch and the power supply.
In the prior art, the resistive load devices are formed after formation of the transistors. After the transistors have been formed, a dielectric layer is deposited and contact openings are formed to the substrate. A second polycrystalline silicon layer is deposited and lightly doped N-type to achieve a resistivity in the range of 10.sup.6 to 10.sup.13 ohms/square. This blanket implant determines the load resistor value. The resistivity of the load resistors must be low enough to supply ample current to compensate for transistor leakages, but high enough to allow for sufficient standby currents for proper device operation under adverse conditions.
Resistance of the polycrystalline silicon load structures is a function of four variables. These are: the grain structure of the polycrystalline silicon used to form the resistor structure, the impurity levels used to dope the polycrystalline silicon; the cross-sectional area of the resistive device; and the length of the device. Impurity levels and polycrystalline silicon grain structure can be controlled only to limits determined by the process technology being used. If cross-sectional area of the structure could be reduced, length of the load resistor could also be reduced to preserve a given resistance for a small overall structure.
It would be desirable to provide a polycrystalline silicon resistor structure, and a method for fabricating same, which resulted in resistor structures having a reduced cross-sectional area. It would further be desirable for such a method to be compatible with existing process technologies.